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25‐2: LTPO TFT Technology for Level Shifter Integrated Gate Driver in UHD 4K Displays
Author(s) -
Rahaman Abidur,
Kim Hyunho,
Jang Jin
Publication year - 2020
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13879
Subject(s) - logic level , cmos , gate driver , thin film transistor , electrical engineering , optoelectronics , materials science , integrated circuit , shift register , logic gate , computer science , computer hardware , electronic circuit , engineering , nanotechnology , voltage , layer (electronics)
We demonstrate the level shifter integrated gate drive circuits using Low‐Temperature Poly‐Si (LTPO) TFT technology. Three level shifters are integrated with a 16‐stage 2‐clock CMOS shift register. A low 5 V start pulse is level up to a high 20 V for gate driving operation. The 4 μs pulse width ensures its speed compatibility to drive an Ultra‐High Definition (UHD) 4K displays (3840 X 2160 @ 60 Hz).