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25‐1: Multi‐bit MIP(Memory‐in‐Pixel)‐based Pixel Circuit of CMOS Backplane for Micro‐LED Display
Author(s) -
Seong Jewoo,
Jang Jinwoong,
Lee Jaehoon,
Lee Myunghee
Publication year - 2020
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13878
Subject(s) - backplane , pixel , cmos , dot pitch , node (physics) , computer science , dissipation , led display , image sensor , electronic engineering , computer hardware , artificial intelligence , engineering , physics , thermodynamics , structural engineering , operating system
The Micro‐LED display is getting more attention in AR/MR (Augmented/Mixed Reality) applications. The display size of 0.5 to 0.7‐inch is preferred with 5,000 or higher PPI (Pixel Per Inch). Due to the pixel density and size, a CMOS (Complementary Metal‐Oxide‐Silicon) backplane is a preferred solution for driving the pixelized micro‐LEDs. This paper proposes a multi‐bit MIP‐based pixel circuit with PWM driving for a CMOS backplane in order to minimize power dissipation. it also provides an estimation of the minimum achievable pixel size based on the CMOS process node.