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P‐8.5: An 8K image processing optimization system based on double FPGA chip
Author(s) -
Liyanfu,
Genglihua,
Maxitong,
Lengchanglin,
Duanran,
Wucongrui
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13665
Subject(s) - computer science , field programmable gate array , embedded system , interface (matter) , computer hardware , protocol (science) , application specific integrated circuit , chip , transmission (telecommunications) , image processing , gate array , image (mathematics) , artificial intelligence , telecommunications , medicine , alternative medicine , bubble , pathology , maximum bubble pressure method , parallel computing
8K Ultra‐High Resolution Display (UHD) system has attracted more and more attention due to its high definition and super sense of presence. In the immature stage of 8K ASIC, using FPGA(Field Programmable Gate Array) for image processing is undoubtedly the most suitable solution.The system adopts two cost‐effective FPGA chip schemes, which do not need to add additional video protocol conversion chip, and uses HDMI2.0 interface IP inside the FPGA to receive video. On this basis, through code optimization, a set of simplified system architecture is built to realize the processing and transmission of 8K and 4K signal sources. The most important feature of the system is to make full use of the energy efficiency of each FPGA chip, and to maximize the savings of board size. The main module of the system include LVDS receiving module, pixel edge transmission module, color space conversion module, image upscaler module, image color processing module, image format conversion module and so on. The main and difficult technologies involved include LVDS interface protocol, v‐by‐one interface protocol, DDR3 reading and writing, HDMI2.0 and v‐by‐one IP fusion technology. This paper will explain the system framework and the function of each module, and focus on the key technologies. At the end of the paper, the resource utilization of the chip are listed.