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P‐5.3: Design of Amorphous Silicon Thin‐Film Transistor Gate Driver Circuit with High Reliability and Narrow Border for Middle Size Liquid Crystal Display
Author(s) -
Ke Jhongciao,
Chung Techen,
Liao Chiate,
Yu Chiamin,
Qiao Yanbing,
Zou Zhongfei,
Guo Xiaojun
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13626
Subject(s) - thin film transistor , materials science , transistor , reliability (semiconductor) , optoelectronics , threshold voltage , amorphous solid , amorphous silicon , node (physics) , liquid crystal display , electrical engineering , silicon , voltage , crystalline silicon , engineering , nanotechnology , layer (electronics) , chemistry , physics , crystallography , power (physics) , structural engineering , quantum mechanics
In this paper, an integrated hydrogenated amorphous silicon (a‐Si: H) thin‐film transistor (TFT) gate driver circuit design with high reliability and the narrow border for middle size liquid crystal display is demonstrated. The circuit design with two sets of the low‐level holding unit can increase the reliability and suppress the threshold voltage (V th ) shift of TFT in the circuit. In addition, the low‐level holding unit is floating in the Q node pre‐charge period, ensuring that the low‐level holding unit can be efficiently turn off during the selected stage working. As a result, the circuit is very stable even at the TFT V th shift of 3V in the high‐temperature operation.