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P‐1.14: The Influence of Bottom gate Dielectric Roughness on the Performance of Double‐Gate a‐IGZO Thin Film Transistors
Author(s) -
Qin Ludong,
Deng Xuan,
Tao Jinao,
Zhang Shengdong
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13608
Subject(s) - materials science , gate dielectric , thin film transistor , dielectric , optoelectronics , gate oxide , surface roughness , amorphous solid , surface finish , plasma enhanced chemical vapor deposition , transistor , threshold voltage , chemical vapor deposition , layer (electronics) , nanotechnology , electrical engineering , composite material , voltage , chemistry , engineering , organic chemistry
In this paper,double gate amorphous indium gallium zinc oxide thin film transistors (a‐IGZO TFTs)are investigated in which we use SiO 2 deposited by plasma enhanced chemical vapor deposition(PECVD) as bottom‐gate dielectric with different roughness measured by AFM. Our results show that the devices with smaller roughness of bottom‐gate dielectric, which is able to decrease the interface scattering between a‐IGZO surface conducting channel and gate dielectric, can get much larger on state currents and bigger field effect mobilities.Besides,the devices still have good interface properties according to hysteresis curves.