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48.1: Invited Paper: A Novel Gate Driver Circuit for Depletion Mode a‐IGZO TFTs
Author(s) -
Oh Jongsu,
Kim Yong-Sang
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13555
Subject(s) - thin film transistor , electrical engineering , threshold voltage , voltage , transistor , node (physics) , optoelectronics , materials science , leakage (economics) , logic gate , power consumption , reliability (semiconductor) , electronic circuit , power (physics) , computer science , engineering , physics , nanotechnology , layer (electronics) , structural engineering , quantum mechanics , economics , macroeconomics
This paper proposes a novel gate driver circuit to realize high reliability using depletion mode a‐InGaZnO thin‐film transistors (TFTs). Using 3T1C circuit configuration, we prevented the leakage path for Q node by realizing gate‐to‐source voltage (V GS ) under 0 V value. The proposed circuit can be operated when the V TH is shifted to ‐3 V from the initial value (V TH = ‐0.35 V). Also, the novel gate driver circuit with the AC driven pull‐down units can maintain the almost same normalized value from ‐1 V to ‐3 V of the V TH shift range when compared to the results of circuit with the DC driven pull‐down units. The proposed circuit can maintain the power consumption within 3.65 times of the normal value at ‐5 V threshold voltage value.