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13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface
Author(s) -
Qin Zhengcai
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13410
Subject(s) - jitter , electronic circuit , computer science , clock recovery , clock signal , interface (matter) , front and back ends , electronic engineering , computer hardware , electrical engineering , engineering , telecommunications , bubble , maximum bubble pressure method , parallel computing , operating system
This work presents a front‐end circuits including of the equalizer and clock/data recovery (CDR) circuits in the source driver ICs (SDICs) for the TFT‐LCD intra‐panel interfaces. For 4K2K LCD TV, the data rate of SDICs has been increased to 5Gbps per lane, so it is a challenge to develop the front‐end circuits when they suffered from the serious ISI and large jitters in received data. In the front‐end circuits meeting the BOE’s CHPI specification, a cascade equalizer are used to widen the eye diagram to reduce BER and a dual loop CDR circuits are used to tolerate the large input jitter and power noise.