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P‐198: Late‐News Poster: Off‐Current Reduction in p‐Type SnO Thin‐Film Transistors through Fermi‐Level Unpinning
Author(s) -
Kim Taikyu,
Kim Jeong-Kyu,
Xu Hongwei,
Yim Sungyeon,
Jeong Jae Kyeong
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.13186
Subject(s) - schottky barrier , optoelectronics , materials science , thin film transistor , transistor , electrode , current (fluid) , fermi level , semiconductor , nanotechnology , electron , electrical engineering , chemistry , voltage , layer (electronics) , engineering , physics , diode , quantum mechanics
High off‐current in p‐type SnO thin‐film transistors (TFTs) limits the application to active matrix devices for next generation display industry. Here, we propose a new approach to suppress the off‐current using metal‐interlayer‐semiconductor (MIS) contact structure. The MIS contact structure makes Fermi‐level pinning (FLP) alleviated through an ultrathin interlayer (IL) which prevents metal‐induced gap states (MIGSs), the origin of severe FLP, and thereby Schottky barrier height (SBH) can be modulated. With the electron SBH (eSBH) increasing, the electron injection from drain electrode into the SnO channel is suppressed, which results in the reduction of the off‐current from 5.1 × 10 ‐8 A to 2.4 × 10 ‐9 A and the enhancement of the I ON/OFF from 2.7 × 10 2 to 2.8 × 10 3 compared with the conventional metal‐semiconductor (MS) contacted TFTs. This work shows not only the enhancement in device performance but also a new perspective on the origin of off‐current in the p‐type SnO TFTs.