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23‐3: Distinguished Paper: The New Route for Realization of 1µm‐pixel‐pitch High Resolution Displays
Author(s) -
Choi Ji Hun,
Yang Jong-Heon,
Pi Jae-Eun,
Hwang Chi-Young,
Kim Yong-Hae,
Kim Gi Heon,
Kim Hee-Ok,
Hwang Chi-Sun
Publication year - 2019
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12920
Subject(s) - pixel , realization (probability) , dot pitch , wafer , line (geometry) , channel (broadcasting) , thin film transistor , resolution (logic) , transistor , high resolution , subthreshold conduction , holography , materials science , computer science , optoelectronics , electrical engineering , computer hardware , optics , physics , engineering , voltage , geology , artificial intelligence , nanotechnology , remote sensing , layer (electronics) , statistics , mathematics , geometry
We present a new pixel structure to realize the 1μm‐pixel‐pitch display. This structure is based on the conventional back‐channel etched thin‐film transistor (TFT), but all layers except the horizontal gate line are vertically stacked on the embedded data line, enabling the implementation of high resolution display panels. The vertically‐stacked TFT with 1μm‐channel length shows a high field effect mobility over 50 cm 2 /Vs, low subthreshold slope of 78 mV/decade. It also shows a high uniform electrical characteristic over the entire 6‐inch wafer. The development of new architecture enables the implementation of a 1μm‐pixel‐pitch high resolution displays such as digital hologram.