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P‐1.6: Effect of Deposition Condition of Passivation Layer on the Performance of Self‐Aligned Top‐Gate a‐IGZO TFTs
Author(s) -
Zhang Xiaodong,
Deng Xuan,
Yang Huan,
Zhang Letao,
Zhang Shengdong
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12774
Subject(s) - passivation , materials science , thin film transistor , optoelectronics , plasma enhanced chemical vapor deposition , layer (electronics) , deposition (geology) , amorphous solid , oxide thin film transistor , chemical vapor deposition , electronic engineering , nanotechnology , chemistry , paleontology , organic chemistry , sediment , engineering , biology
In this paper, we fabricated self‐aligned top‐gate (SATG) amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs). The conductive source/drain regions were formed by hydrogen incorporation during the deposition of SiOx or SiNx passivation layer using plasma‐enhanced chemical vapor deposition (PECVD). The effect of passivation layer deposition condition on the electrical performance of self‐aligned top‐gate a‐IGZO TFTs was investigated. It was shown that the source‐drain parasitic resistance (Rsd) was effectively reduced during the deposition of SiNx passivation layer than SiO x . However, as the deposition temperature of SiN x passivation layer increased, hydrogen lateral diffusion into channel region resulted in the shrinkage of effective channel length and the deterioration of electrical performance of short‐channel device.