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8.1: Invited Paper: Enhanced Elevated‐Metal Metal‐Oxide Thin‐Film Transistor Technology
Author(s) -
Lu Lei,
Li Jiapeng,
Xia Zhihe,
Wang Sisi,
Kwok Hoi Sing,
Wong Man
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12644
Subject(s) - thin film transistor , materials science , transistor , optoelectronics , annealing (glass) , oxide , parasitic capacitance , metal , capacitance , thin film , nanotechnology , electrical engineering , metallurgy , layer (electronics) , engineering , electrode , chemistry , voltage
Enhancement to the elevated‐metal metal‐oxide (EMMO) thin‐film transistor (TFT) architecture employing annealing‐induced source/drain regions is presently reported, thus further extending the advantage of EMMO over the conventional TFT architectures. The enhancement includes: a 3‐mask process resulting in a reduced mask‐count, hence manufacturing cost; a bottom‐gate self‐aligned process resulting in reduced parasitic overlap capacitance, hence signal delay; and a 3000‐°C process, with the lower temperature offering better compatibility with a wider range of flexible substrates.