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P‐194: Late‐News Poster: Self‐Aligned Double‐Gate Cu‐MIC Poly‐Ge 1‐x Sn x Thin‐Film Transistors on a Glass Substrate
Author(s) -
Nishiguchi Naoki,
Miyazaki Ryo,
Utsumi Hiroki,
Hara Akito
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12444
Subject(s) - thin film transistor , materials science , amorphous solid , substrate (aquarium) , crystallization , transistor , thin film , optoelectronics , sputtering , fabrication , copper , germanium , analytical chemistry (journal) , nanotechnology , crystallography , silicon , layer (electronics) , chemical engineering , metallurgy , electrical engineering , chemistry , voltage , oceanography , engineering , geology , alternative medicine , pathology , chromatography , medicine
In this study, we fabricated p‐channel (p‐ch) poly‐Ge 1‐x Sn x thin‐film transistors (TFTs) on glass substrates using three key technologies. They are the self‐aligned double‐gate (DG) structure, metal‐induced crystallization using copper (Cu‐MIC), and aluminum‐induced lateral metallization source drain (Al‐LM‐SD). An amorphous Ge 1‐x Sn x film, which was prepared using a sputtering target with x=0.02 and 0.07, was crystallized by Cu MIC at 500 °C, and it was observed that Cu‐MIC enables us to fabricate a high‐quality poly‐Ge 1‐x Sn x thin film. The self‐aligned DG Cu‐MIC p‐ch poly‐Ge 1‐x Sn x TFTs, with x=0.02 and 0.07, achieved mobility of 18 and 25 cm 2 /Vs, respectively. Our proposed p‐ch TFT will facilitate fabrication of hybrid CMOS with n‐ch indium‐gallium‐zinc‐oxide TFT.