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46‐4: 513‐ppi Hybrid Display with Stacked Transistors
Author(s) -
Mori Hidenori,
Shima Yukinori,
Hosaka Yasuharu,
Okazaki Kenichi,
Kusunoki Koji,
Shishido Hideaki,
Hatsumi Ryo,
Yoshitomi Shuhei,
Yamazaki Shunpei
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12406
Subject(s) - stacking , materials science , reliability (semiconductor) , transistor , optoelectronics , luminance , visibility , power consumption , diode , thin film transistor , power (physics) , computer science , optics , electrical engineering , nanotechnology , engineering , chemistry , artificial intelligence , layer (electronics) , physics , voltage , organic chemistry , quantum mechanics
A process for stacking two layers of transistors is used to form a high‐resolution hybrid display with improved reliability of an organic light‐emitting diode. Sufficient visibility and low power consumption are achieved by changing the display mode in accordance with ambient luminance.

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