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P‐61: Investigation of IC Position for Reducing Chip‐on‐Glass Mura by Quantified Model
Author(s) -
Jia Qian,
You Jaegeon,
Li Hongmin,
Dong Zhifu,
Wang Xinxing,
Zhan Yucheng,
Zhang Bin,
Sun Xuefei,
Xu Xiaona,
Yao Jikai
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12206
Subject(s) - mura , materials science , thermal expansion , finite element method , chip , substrate (aquarium) , leakage (economics) , anisotropy , composite material , thermal , mechanical engineering , optoelectronics , electronic engineering , structural engineering , electrical engineering , optics , engineering , liquid crystal display , thermodynamics , physics , oceanography , economics , macroeconomics , geology
The aim of this work is to identify the optimum position of the driver‐ICs on the panel, using finite element analysis and experiments with 10.1″ and 13.3″ panels. The mismatch of coefficient of thermal expansion of the IC and anisotropic conductive bonding film and glass is considered as the major driver inducing thermal stress, substrate warpage, light leakage, and finally mura.