Premium
P‐54: A Low‐Power Time‐Interleaving Analog Adder for Externally Compensated AMOLED/Micro‐LED Displays
Author(s) -
Qiu Hezi,
Lu Wengao,
Zhang Shengdong,
Jiao Hailong
Publication year - 2018
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.12177
Subject(s) - adder , interleaving , amoled , computer science , electronic engineering , glitch , pipeline (software) , analog multiplier , power consumption , serial binary adder , power (physics) , computer hardware , electrical engineering , analog signal , materials science , engineering , cmos , digital signal processing , physics , layer (electronics) , quantum mechanics , active matrix , composite material , programming language , thin film transistor
A novel time‐interleaving analog adder used in externally compensated AMOLED/Micro‐LED systems is proposed. With a specialized pipeline architecture, the analog adder achieves lower power consumption and higher precision of digital‐to‐analog conversion. The maximum output error of the analog adder is only 3 mV while the nonlinear error is 0.0735%.