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P‐28: Robust Gate Driver Design with Etching‐Stop‐Layer Type InGaZnO TFTs Using Stack Buffer Structure
Author(s) -
Liao Congwei,
Ma Yihua,
Liu Xiaodi,
Liu Xiang,
Zhang Shengdong
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11883
Subject(s) - thin film transistor , stack (abstract data type) , capacitance , materials science , optoelectronics , layer (electronics) , buffer (optical fiber) , etching (microfabrication) , electronic engineering , amoled , parasitic capacitance , computer science , electrical engineering , engineering , nanotechnology , chemistry , electrode , programming language , active matrix
A stack buffer structure is proposed to suppress feed‐through effects, which is caused by serious gate‐to‐drain capacitance of Etching‐Stop‐Layer (ESL) type InGaZnO (IGZO) TFTs. For low‐level‐maintaining periods, the stack buffer TFT can be modeled by reversely cascaded diodes for decreasing of noise voltage of internal nodes. Compared with conventional designs, the proposed buffer structure owns better stability and good driving ability. A robust gate driver using the proposed buffer structure is demonstrated, and only 7 TFTs and 1 capacitance are used. Thorough analysis and simulations are carried out, and the circuit performance is discussed concerning threshold voltage variation, different bootstrapping capacitance, and decreased driving pulse width. It is proven that the proposed gate driver is promising for high performance IGZO TFT display with high resolution for large dimension display.