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P‐15: Prediction Method of Device Instability in a‐InGaZnO TFTs under Positive Gate Biases and Thermal Stresses using TCAD Simulation
Author(s) -
Kim Jin-young,
Tak Nam-kyun,
Choi Jin-hyung,
Lee Won-seok,
Cho Won-ju,
Park Jong-tae
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11869
Subject(s) - thin film transistor , materials science , threshold voltage , optoelectronics , technology cad , thermal , amorphous solid , transistor , dielectric , electronic engineering , voltage , electrical engineering , layer (electronics) , nanotechnology , engineering , chemistry , physics , thermodynamics , organic chemistry , engineering drawing , cad
The experimental and modeling study of bias and thermal stresses induced threshold voltage shift (ΔV TH ) in amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin film transistors (TFTs) has been investigated. The evolution of ΔV TH under positive biases and thermal stresses is dominated by charge trapping effect at channel and gate dielectric interface. We can predict the ƊV TH under different bias and thermal stresses using technology computer aided design (TCAD) device simulation if one measures once the device degradation at particular bias and temperature. Using this method, one can optimize the supply bias voltage and extend to predict the device lifetime.