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76‐2: Field‐Effect Transistor with CAAC/CAC‐OS Double‐Layer Structure for Diversion of Gen 8‐10.5 Amorphous Silicon Production Lines
Author(s) -
Okazaki Kenichi,
Shima Yukinori,
Kurosaki Daisuke,
Nakazawa Yasutaka,
Koezuka Junichi,
Baba Haruyuki,
Yamazaki Shunpei
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11829
Subject(s) - materials science , amorphous silicon , amorphous solid , layer (electronics) , silicon , optoelectronics , transistor , field effect transistor , reliability (semiconductor) , electrical engineering , nanotechnology , crystalline silicon , engineering , crystallography , chemistry , physics , power (physics) , quantum mechanics , voltage
Using an active layer in which a c‐axis‐aligned crystalline oxide semiconductor (CAAC‐OS) is stacked on a cloud‐aligned composite OS (CAC‐OS), we have succeeded in fabricating a channel‐etched field‐effect transistor (CE‐FET) with a high on‐state current and favorable reliability. The CE‐FET with the CAAC/CAC‐OS structure can be fabricated using the existing amorphous silicon facilities and processes almost as they are. Therefore, we believe that high‐performance devices can be fabricated at low cost with large Gen 8‐10.5 glass substrates.