Premium
16‐2: Cost‐effective Driver IC Architecture using Low‐power Memory Interface for Mobile Display Application
Author(s) -
Hwang Moon-Sang,
Choe Deok-Jun,
Kim Do-Wan,
Park Joon-Bae,
Bae Jun-Woo,
Choe Won-jun,
Kwag Jin Oh
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11645
Subject(s) - power consumption , computer science , interface (matter) , computer hardware , power (physics) , embedded system , architecture , operating system , art , physics , bubble , quantum mechanics , maximum bubble pressure method , visual arts
Cost‐effective Display Driver IC architecture with an external memory is presented. Low‐power and high‐speed memory interface is proposed to minimize the increase of power consumption and the number of pins. The measured power consumption was less than 45mW with four 1.6Gbps data lanes, 1 clock lane and 1 command lane.