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9‐5L: Late‐News Paper : 6Gb/s Ultra Definition Display Interface (UDDI) for Large‐size 8K Displays
Author(s) -
Amirkhany Amir,
Hekmat Mohammad,
Sankaranarayanan Sabarish,
Jose Anup,
Abramzon Valentin,
Jaffari Nancy,
Saito Keisuke,
Elzeftawi Mohamed,
Wang Michael,
Moballegh Shiva,
Malhotra Gaurav,
Kamali Jalil,
Xiong Wei
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11592
Subject(s) - jitter , computer science , transmitter , interface (matter) , computer hardware , transmission (telecommunications) , phase locked loop , equalization (audio) , channel (broadcasting) , electronic engineering , real time computing , engineering , telecommunications , bubble , maximum bubble pressure method , parallel computing
A 6Gb/s per lane ultra‐definition display interface (UDDI) system is presented to reduce the production cost and to improve the form‐factorof Quad‐UHD TV panels. The receiver (RX) is implemented in a 0.18um Source IC process. The transmitter (TX) is fabricated in a low‐leakage 65nm process for integration with a Timing Controller (TCON) ASIC. The analog front‐end of the receiver is equipped with a continuous‐time linear equalizer and a 5‐tapdecision feedback equalizer. Continuous calibration and adaptation engines in the receiver ensure reliable communication over an extended operation period. The transmitter employs 3‐tap pre‐emphasis for channel equalization and a dual‐VCO LC PLL for low jitter transmission. System link layer employs a low‐overheaderror correction code to protect video data against random errors and to limit worst‐case run‐length. The system also deploys scrambling to reduce EMI. Noise‐free video quality was achieved at 6Gb/s over 65” display Source PCBs and at 4Gb/s over 105” display Source PCBs. The UDDI system improves the highest existing intra‐panel interface speed by nearly a factor of 2.