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7‐2: Design of Highly Reliable Depletion‐Mode a‐IGZO TFT Gate Driving Circuit for 31‐in. 8K4K 287‐ppi TFT‐LCD
Author(s) -
Shi Long-Qiang,
Chen Shu-Jhih,
Chou Yi-Fang,
Zeng Li-Mei,
Zeng Mian,
Wang Tian-Hong,
Chen Ren-Lu,
Liao Cong-Wei,
Lv Xiao-Wen,
Li Wen-Ying,
Liu X,
Lee Chia-Yu
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11561
Subject(s) - thin film transistor , transistor , threshold voltage , liquid crystal display , spice , voltage , node (physics) , electrical engineering , materials science , electronic engineering , optoelectronics , engineering , structural engineering , layer (electronics) , composite material
In this paper, high reliable a‐IGZO TFT gate driving circuit was designed. Series‐connected two‐transistor (STT) structure and dual low‐voltage‐level power signal (Vss) were used to solve the initial negative Vth of IGZO TFTs. Special pull‐down holding part was designed for wider Vth shift window during panel operation. The Vth shift margin of this proposed GOA design is from ‐5V to +9V by using Eldo‐Spice simulation system. In addition, the pull‐up control part could also play a role to pull the Q node voltage down and it is helpful for narrow border design. Finally, a 31‐in. 8K4K 287‐ppi TFT‐LCD was successfully demonstrated based on the study above.