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7‐1: Invited Paper : Application of Low‐Frequency Clock Signals to Gate Driver Circuits
Author(s) -
Lin Chih-Lung,
Cheng Mao-Hsun
Publication year - 2017
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.11559
Subject(s) - electronic circuit , electrical engineering , power consumption , gate driver , clock signal , transistor , electronic engineering , power (physics) , thin film transistor , computer science , engineering , voltage , materials science , physics , layer (electronics) , quantum mechanics , composite material
This paper collates design concepts of low‐power gate driver circuits, and our related work is reviewed. Many approaches to power consumption amelioration have been developed and focus on different parts of circuit structures. Recently, low‐frequency clock signals are adopted to further reduce both power consumption and thin‐film transistor (TFT) threshold voltage shifts (ΔV TH ).