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P‐15: AZO Etch Buffer Layer based Back‐Channel‐Etch a‐IGZO TFT Technology
Author(s) -
Song Zhen,
Wang Guoying,
Xiao Xiang,
Deng Wei,
Zhang Shengdong
Publication year - 2016
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10869
Subject(s) - thin film transistor , materials science , optoelectronics , layer (electronics) , etching (microfabrication) , transistor , amorphous solid , oxide thin film transistor , stress (linguistics) , threshold voltage , oxide , nanotechnology , electrical engineering , voltage , chemistry , crystallography , metallurgy , engineering , linguistics , philosophy
A new back‐channel‐etch (BCE) process for fabricating amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin film transistors (TFTs) is demonstrated. The damage‐free back channel surface by using Al‐doped ZnO (AZO) transparent conducting oxide (TCO) as the S/D etch buffer layer can be achieved successfully and the fabricated BCE‐type a‐IGZO TFTs show excellent electrical performance and gate bias‐stress stability. The major performance parameters include a subthreshold swing SS of 0.19V/decade, µ FE of 10.7cm 2 /V‐s, I on /I off of 1.5×10 10 , and V TH shift of less than ± 0.5V under gate‐bias stress. These results show that the proposed BCE‐type process for fabricating a‐IGZO TFTs is feasible.