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P‐12: 3‐D TCAD Simulation for Describing Intrinsic Fluctuations in Polycrystalline Silicon Thin Film Transistors
Author(s) -
Jang Seunghyun,
Son ByoungTaek,
Choi Sung-Hwan,
Kim Dongjo,
Kim Gunshik,
Yoo Moon-Hyun
Publication year - 2016
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10856
Subject(s) - thin film transistor , materials science , polycrystalline silicon , grain boundary , active matrix , amoled , optoelectronics , annealing (glass) , crystallite , silicon , voronoi diagram , transistor , nanocrystalline silicon , diode , crystalline silicon , composite material , electrical engineering , voltage , amorphous silicon , metallurgy , microstructure , geometry , layer (electronics) , engineering , mathematics
In this work, we investigate the influence of grain boundaries on the performance of polycrystalline silicon thin‐film transistors (poly‐Si TFTs) for high resolution active‐matrix organic light‐emitting diode (AMOLED) displays using Voronoi diagram. The novel 2‐D Voronoi polycrystalline grain structure can show a more realistic electrical parameter variability when the channel dimension is scaled down for high‐resolution display. Using a proposed method, the impact of polycrystalline granular structure controlled by crystallization process is identified. Further, we predict the effect of grain boundary‐induced variations under different laser annealing process, such as Excimer Laser Annealing (ELA).