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P‐4: Electrical Characteristics of Dual‐Gate CAAC‐IGZO FET with Self‐Aligned Top Gate
Author(s) -
Honda Ryunosuke,
Suzuki Akio,
Matsuda Shinpei,
Saito Satoru,
Shima Yukinori,
Koezuka Junichi,
Yamazaki Shunpei
Publication year - 2016
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10821
Subject(s) - materials science , optoelectronics , capacitance , dual (grammatical number) , current (fluid) , electrical engineering , chemistry , engineering , electrode , art , literature
We fabricated dual‐gate CAAC‐IGZO FETs with self‐aligned top gates and investigated their electrical characteristics. The drain current was larger than expectedfrom the GI capacitance ratio to single‐gate FETs. Device simulation results suggest that shallow trap states and increase in electron mobility by self‐heating of FETs can explain the large drain current.