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21.3: A Novel 5‐Mask Etch‐Stopper Pixel Structure with A Short Channel Oxide Semiconductor TFT
Author(s) -
Yang JoonYoung,
Jung SungHoon,
Woo ChangSeung,
Lee JuYun,
Jun Myungchul,
Kang InByeong,
Park JungHo
Publication year - 2015
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10477
Subject(s) - thin film transistor , pixel , materials science , channel (broadcasting) , optoelectronics , capacitance , layer (electronics) , parasitic capacitance , electrical engineering , computer science , nanotechnology , chemistry , engineering , artificial intelligence , electrode
In order to solve the main issues of etch‐stopper (ES) pixel structure (mask steps, parasitic capacitance C gs , TFT channel length) in a‐IGZO pixel structure of AMLED, new 5‐mask ES a‐IGZO pixel structure was investigated. TFT channel length of 5 µm could be achieved by self‐aligned damage preventing layer. We could achieve good characteristics and reliability of short‐channel‐length (under 5 µm) ES TFTs. And also C gs could be reduced more than 30%.