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69.3: a‐IGZO TFTs Reliability Improvement by Dual Gate Structure
Author(s) -
Chang KuoJui,
Chen WenTai,
Chang WeiCheng,
Chen WenPin,
Nien ChengChung,
Shih TsungHsiang,
Lu HsuehHsing,
Lin YuHsin
Publication year - 2015
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10353
Subject(s) - materials science , thin film transistor , optoelectronics , stress (linguistics) , reliability (semiconductor) , threshold voltage , amorphous solid , transistor , voltage , electrical engineering , nanotechnology , crystallography , chemistry , layer (electronics) , engineering , linguistics , philosophy , power (physics) , physics , quantum mechanics
The positive bias thermal stress (PBTS), negative bias thermal stress (NBTS) and negative bias illumination stress (NBIS) stabilities of dual gate amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) thin film transistors via applying different top gate voltage is concentrated in this paper. These dual gate devices show better PBTS/NBTS stress stabilities (smaller ΔV th shift) than conventional bottom gate TFT device. Additionally, these dual gate devices also exhibits better NBIS stress results than conventional bottom gate TFT device.