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65.2: Invited Paper : Bias‐Stress‐Induced Charge Trapping in Flexible Polymer Gate Dielectrics in Organic TFTs
Author(s) -
Kang Boseok,
Choi Hyun Ho,
Cho Kilwon
Publication year - 2015
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10279
Subject(s) - dielectric , thin film transistor , materials science , trapping , optoelectronics , gate dielectric , transistor , charge (physics) , stress (linguistics) , organic semiconductor , semiconductor , polymer , electrical engineering , nanotechnology , voltage , layer (electronics) , composite material , physics , engineering , ecology , linguistics , philosophy , quantum mechanics , biology
Recent studies by our group on bias‐stress‐driven electrical instabilities in organic thin‐film transistors (OTFTs) are described. When OTFTs are operated under continuous gate and source/drain biases, the resulting bias stresses can degrade overall device performance. Here, general methods for analyzing such bias instabilities are introduced. Based on these methods, it is demonstrated that the polymer chain ends of polymer gate dielectrics can act as charge trapping sites. Furthermore, a new strategy for analyzing charge traps at the semiconductor‐dielectric interface is introduced.