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P‐39: High Speed and Power‐Saving Interface for High‐Resolution and Low Power Display Panel
Author(s) -
Liu HsiEn,
Su ChunJen,
Cheng ChihKang,
Liu WenKuen
Publication year - 2015
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10095
Subject(s) - interface (matter) , power (physics) , computer science , process (computing) , voltage , power consumption , computer hardware , point (geometry) , channel (broadcasting) , high resolution , electrical engineering , embedded system , real time computing , engineering , telecommunications , operating system , physics , remote sensing , bubble , quantum mechanics , maximum bubble pressure method , geology , geometry , mathematics
An 8‐bit, 1446‐channel source driver IC for the 2K resolution application has been presented. The proposed source IC adopts the point‐to‐point (P2P) interface with the embedded clock to achieve the high video data rate requirement. The fine‐grained control has also been developed for the interface to operate with very low power consumption, which is as low as one‐fourth that of the traditional design. The source driver is implemented in a 0.15 m 1.8V/13.5V high‐voltage process. The maximum data rate with a 1.8V supply voltage is up to 2.25Gbps.