Premium
P‐37: A 5 Gbps/lane Intra‐Panel Interface for Ultra‐High‐ Definition TFT‐LCD Application
Author(s) -
Kang YuChi,
Chang LiWei,
Wu YungChih,
Chen WeiTing,
Ho ChiaPu,
Yang ChihHsiang
Publication year - 2015
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/sdtp.10090
Subject(s) - field programmable gate array , interface (matter) , computer science , encoder , phase locked loop , computer hardware , point to point , point (geometry) , embedded system , topology (electrical circuits) , operating system , engineering , computer network , electrical engineering , jitter , telecommunications , geometry , mathematics , bubble , maximum bubble pressure method
This paper presents a high speed intra panel interface which applies point to point topology, phase locked loop (PLL) type clock data recovery (CDR) and DC self‐adjusting data encoder. The preliminary measurement result on Altera stratix5 FPGA platform shows that the maximum data rate can be operated up to 5Gbps/lane.