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Evaluation of the hot‐carrier‐induced offset voltage of differential pairs in analogue CMOS circuits
Author(s) -
Thewes Roland,
Kivi Michael J.,
Goser Karl F.,
Weber Werner
Publication year - 1995
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680110411
Subject(s) - cmos , offset (computer science) , extrapolation , input offset voltage , electronic engineering , electronic circuit , voltage , threshold voltage , differential (mechanical device) , materials science , electrical engineering , computer science , engineering , mathematics , operational amplifier , transistor , statistics , amplifier , programming language , aerospace engineering
Using a specifically developed measurement set‐up and a test structure typical for analogue applications, high precision measurements of the stress‐induced offset voltage degradation of differential pairs are presented. Extrapolation to operating conditions yields valuable information for analogue design in the sub‐micron CMOS regime.