Premium
Use of a cmos static memory array as a technology test vehicle
Author(s) -
SchmittLandsiedel D.,
Winnerl J.,
Neuendorf G.,
Kölzer J.
Publication year - 1992
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680080309
Subject(s) - static random access memory , cmos , testability , design for testing , electronic engineering , limiting , engineering , electronic circuit , computer science , reliability engineering , embedded system , electrical engineering , mechanical engineering
A static memory array is described for use as a test vehicle in CMOS process development. Design guidelines are given for a large operating range and good testability. Address paths are defined for efficient comparison of access time measurements and simulations. the functional yield of SRAMs is correlated with defect density results from test structures to identify the relevant yield limiting defects. It is shown that an SRAM is a suitable test vehicle for yield prediction of complex CMOS random logic circuits.