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Evolution of VLSI reliability engineering
Author(s) -
Crook D. L.
Publication year - 1991
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680070406
Subject(s) - reliability (semiconductor) , failure rate , very large scale integration , reliability engineering , computer science , microcomputer , product (mathematics) , projection (relational algebra) , engineering , embedded system , chip , mathematics , telecommunications , algorithm , power (physics) , physics , geometry , quantum mechanics
Projection indicates that by the turn of the century microcomputer chips will have 100 million transistors and failure rates of less than 10 FIT. Traditional accelerated product life tests and wafer level reliability measurement techniques being developed at present will have severe limitations in resolving the 10 FIT failure rate of complex VLSI circuits. This paper discusses these limitations along with the change in direction that the reliability engineering and manufacturing community will have to take over the next decade to meet the challenge of continuously decreasing failure rate goals.