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Reliability characterization of a 3‐mum cmos/sos process
Author(s) -
Dugan M. Patrick
Publication year - 1987
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680030207
Subject(s) - microelectronics , cmos , reliability (semiconductor) , reliability engineering , engineering , electronic engineering , stress (linguistics) , electrical engineering , biasing , voltage , power (physics) , physics , quantum mechanics , linguistics , philosophy
A continuing study of advanced short‐channel CMOS/SOS arrays has been carried out at the RCA Microelectronics Center (MEC) and at RCA Laboratories, Princeton, NJ, since 1981. A technique to assess the reliability of a new process relatively quickly consists of high‐tempertaure accelerated stress testing of ICs by maintaining the temperature at 200°C, while biasing half the inputs at the positive supply voltage and half at ground. The results of these accelerated stress tests together with device analysis, were used to calculate a failure rate and to determine that time‐dependent dielectric breakdown (TDDB) is the principal failure mechanism. No mechanism unique to the CMOS/SOS technology has been observed.