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Surface mount digital package reliability
Author(s) -
Roesch William J.
Publication year - 1986
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680020404
Subject(s) - surface mount technology , reliability (semiconductor) , quad flat no leads package , mount , surface (topology) , electronic packaging , structural engineering , materials science , engineering , mechanical engineering , electronic engineering , composite material , soldering , mathematics , geometry , physics , adhesive , power (physics) , layer (electronics) , quantum mechanics
This paper compares the reliability of four surface mount package styles with the standard through‐hole package. Three test boards were fabricated and subjected to environmental and electrical stresses. The relative package performances of SOICs, butt‐soldered DIPs, surface mounted DIPS, and through‐hole DIPs were found to be equal when subjected to stresses exceeding those expected in normal use. PLCC packages were found to be slightly less reliable in humidity environments than the other packages.