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Reliability analysis of fault tolerant memory arrays
Author(s) -
Nachlas Joel A.
Publication year - 1985
Publication title -
quality and reliability engineering international
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.913
H-Index - 62
eISSN - 1099-1638
pISSN - 0748-8017
DOI - 10.1002/qre.4680010309
Subject(s) - reliability engineering , fault tolerance , measure (data warehouse) , reliability (semiconductor) , weibull distribution , function (biology) , fault (geology) , computer science , feature (linguistics) , hazard , stuck at fault , fault model , electronic engineering , fault detection and isolation , engineering , power (physics) , mathematics , statistics , data mining , electrical engineering , electronic circuit , artificial intelligence , philosophy , actuator , linguistics , chemistry , biology , evolutionary biology , geology , quantum mechanics , physics , organic chemistry , seismology
A model is developed to represent computer memory module reliability as a function of memory array reliability under a fault tolerant design. The fault tolerance feature of the array actually results from a revision in the use of the array so that with respect to some failure modes, the array becomes a K out of N rather than a series system. The model is used to determine array reliability under fault tolerance. The ratio of module reliability under fault tolerance to that without this feature is used as a measure of the benefits of revising array use. A key feature of the analysis is the fact that not all faults can be tolerated. The elemental memory devices examined conform to a decreasing Weibull hazard model. Consequently, evaluation of the general model for the K out of N system realized must be done numerically. However, for the special case in which K=N ‐1, a closed form expression for the performance measure is obtained. This special case occurs for the application of interest and it is shown that the performance measure always exceeds one and depends directly upon the proportion of faults that can be tolerated. Thus the value of fault tolerance is shown to depend upon the extent to which the array will tolerate faults. This provides a basis for deciding whether or not fault tolerance should be implemented.