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Electro‐Physical Properties of Gate‐Last Silicon MOSFETs with Low‐Temperature SiO x N y /HfO x Stack After Ultra‐Shallow Fluorine Implantation from RF Plasma
Author(s) -
Mroczyński Robert,
Jasiński Jakub
Publication year - 2018
Publication title -
physica status solidi (rrl) – rapid research letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.786
H-Index - 68
eISSN - 1862-6270
pISSN - 1862-6254
DOI - 10.1002/pssr.201800152
Subject(s) - materials science , optoelectronics , dielectric , silicon , etching (microfabrication) , mosfet , stack (abstract data type) , reactive ion etching , gate dielectric , semiconductor , field effect transistor , electron mobility , analytical chemistry (journal) , transistor , layer (electronics) , nanotechnology , electrical engineering , chemistry , engineering , voltage , chromatography , computer science , programming language
Ultra‐shallow fluorine implantation from radio frequency (RF) plasma performed in reactive ion etching (RIE) reactor at room temperature (RT) is adopted to metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) technology on silicon (Si) substrates with gate‐last low‐temperature SiO x N y /HfO x double‐gate dielectric stack. The implantation technology is optimized in order to get the maximum fluorine concentration very close to the silicon sub‐surface region. The electrical characterization of fabricated structures reveals an improved quality of the semiconductor/dielectric interface, i.e., lower interface state density ( N it ), effective charge ( Q eff ) and, as a consequence, enhanced mobility ( μ eff ) value and lower sub‐threshold swing (SS) of the investigated MOSFETs. The presented findings are promising for possible applications of fluorine implantation from RF plasma in modern semiconductor devices.