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Impact of an Interfacial Layer on the Electrical Performance of p‐Channel Tin Monoxide Field‐Effect Transistors
Author(s) -
Han Sang Jin,
Kim Sungmin,
Jeong Jae Kyeong,
Kim Hyeong Joon
Publication year - 2017
Publication title -
physica status solidi (rrl) – rapid research letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.786
H-Index - 68
eISSN - 1862-6270
pISSN - 1862-6254
DOI - 10.1002/pssr.201700213
Subject(s) - tin , materials science , monoxide , transistor , threshold voltage , field effect transistor , optoelectronics , dielectric , analytical chemistry (journal) , voltage , electrical engineering , chemistry , metallurgy , chromatography , engineering
This study examined the insertion effect of an interfacial, 7‐nm‐thick SiN x and SiOF layer on the performance of p‐channel tin monoxide (SnO) field‐effect transistors (FETs). The control SnO FETs, which had a thermal SiO 2 gate dielectric, exhibited a mobility, gate swing, threshold voltage ( V TH ) and I ON/OFF ratio of 2.8 cm 2 V −1 s −1 , 6.9 V decade −1 , 19.0 V, and 1.8 × 10 3 , respectively. The SiN x ‐inserted SnO FETs showed a loss in drain current modulation due to the creation of interfacial trap states. In contrast, the gate swing and V TH values were improved substantially to 5.4 V decade −1 and 2.0 V for the SiOF‐inserted SnO FETs, respectively, whereas the comparable mobility and I ON/OFF ratio were preserved. The rationale of the improvement is discussed with respect to Fermi‐energy pinning based on the valence band spectra.