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Multi‐bit storage in reset process of Phase Change Access Memory (PRAM)
Author(s) -
Zhang Yi,
Feng Jie,
Zhang Yin,
Zhang Zufa,
Lin Yinyin,
Tang Ting'ao,
Cai Bingchu,
Chen Bomy
Publication year - 2007
Publication title -
physica status solidi (rrl) – rapid research letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.786
H-Index - 68
eISSN - 1862-6270
pISSN - 1862-6254
DOI - 10.1002/pssr.200600020
Subject(s) - reset (finance) , phase change memory , materials science , phase change , layer (electronics) , amorphous solid , crystallite , bit (key) , process (computing) , phase (matter) , memory cell , phase change material , optoelectronics , computer science , electrical engineering , composite material , chemistry , crystallography , engineering physics , transistor , physics , metallurgy , engineering , operating system , organic chemistry , economics , computer security , voltage , financial economics
A Phase Change Access Memory (PRAM) cell with stacked phase‐change layers and heater layers is prepared. Multi‐bit storage in the reset process of the PRAM is realized by this stacked structure including phase‐change layers with uniform thickness and heater layers with different thickness. The thermal simulation results show three phase‐change layers in three temperature zones, and they will transform from polycrystalline to amorphous state layer by layer. There are four levels of resistance appearing in the R – V characteristics, and 2‐bit storage is realized. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)