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Monolithic Integrated AlGaN/GaN Power Converter Topologies on High‐Voltage AlN/GaN Superlattice Buffer
Author(s) -
Moench Stefan,
Müller Stefan,
Reiner Richard,
Waltereit Patrick,
Czap Heiko,
Basler Michael,
Hückelheim Jan,
Kirste Lutz,
Kallfass Ingmar,
Quay Rüdiger,
Ambacher Oliver
Publication year - 2021
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.202000404
Subject(s) - materials science , optoelectronics , buffer (optical fiber) , voltage , leakage (economics) , gallium nitride , substrate (aquarium) , superlattice , high voltage , biasing , diode , transistor , topology (electrical circuits) , electrical engineering , layer (electronics) , nanotechnology , engineering , oceanography , geology , economics , macroeconomics
A high‐voltage AlN/GaN superlattice (SL) buffer for monolithic AlGaN/GaN power circuits is experimentally compared with a step‐graded AlGaN/GaN buffer. The SL as part of a 5.1 μm epitaxial stack withstands over 1.3 kV. Although the step‐graded buffer is sufficient for low‐side circuits, the operation voltage of monolithic topologies such as a half‐bridge is limited: static negative back gating at −200 V depletes the lateral channel completely. Asymmetrical buffer leakage at a positive substrate voltage of +250 V limits the operation voltage further. The SL buffer mitigates both effects: a negative substrate voltage of −200 V reduced the lateral channel current only by 25%. However, this condition is not required for half‐bridge operation on the SL, because low symmetrical vertical buffer leakage at substrate voltages of ±500 V allows operation of power topologies with positive substrate bias. High‐electron‐mobility transistors (HEMTs) on the graded buffer show excessive threshold voltage shift at negative substrate bias. On the SL buffer, the threshold voltage is shifted only +1 V from negative substrate biases, which allows monolithic high‐voltage power topology operation. 98.8% efficient operation of a 6 × 4 mm 2 GaN‐on‐Si power integrated circuit with a monolithic half bridge, freewheeling diodes, and drivers is demonstrated on the SL.