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Impact of Reduced Gate‐to‐Source Spacing on Indium Phosphide High Electron Mobility Transistor Performance
Author(s) -
Calvo Ruiz Diego,
Han Daxin,
Bonomo Giorgio,
Saranovac Tamara,
Ostinelli Olivier,
Bolognesi Colombo R.
Publication year - 2021
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.202000191
Subject(s) - indium phosphide , transistor , cutoff frequency , optoelectronics , materials science , offset (computer science) , oscillation (cell signaling) , electrical engineering , and gate , logic gate , gallium arsenide , engineering , chemistry , voltage , computer science , biochemistry , programming language
Indium phosphide (InP)‐based high electron mobility transistors (HEMTs) with an offset gate enable higher maximum oscillation frequency ( f MAX ) values because of the resulting reduction in gate‐to‐source resistance. Following this approach, improved direct current (DC) characteristics and cutoff frequencies ( f T / f MAX > 410/710 GHz with L G = 50 nm) are shown with respect to centered gate devices. However, HEMTs with an offset gate show degraded noise performances compared with centered gate devices because of a higher gate leakage current. The results show that offsetting the gate closer to the source is not desirable for ultra‐low‐noise performance.