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High‐Performance Back‐Channel‐Etched Thin‐Film Transistors with an InGaO/InZnO Stacked Channel
Author(s) -
Zhao Mingjie,
Zhang Zewang,
Xu Yingchao,
Xu Daisheng,
Zhang Jiyan,
Huang Zhangchao
Publication year - 2020
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201900773
Subject(s) - thin film transistor , materials science , optoelectronics , transistor , etching (microfabrication) , threshold voltage , electrode , channel (broadcasting) , layer (electronics) , subthreshold conduction , contact resistance , voltage , electrical engineering , composite material , chemistry , engineering
Back‐channel‐etched (BCE) thin‐film transistors (TFTs) with an InGaO/InZnO stacked channel are developed, in which the InGaO and InZnO provide a highly acid‐resistant back channel and a high‐mobility front channel, respectively. The electrical performance of the TFT is optimized by adjusting the InGaO thickness. The best performance is achieved for the TFT with 10 nm thick InGaO. A thinner InGaO layer leads to inferior performance due to damage during the back‐channel‐etching process, while a thicker InGaO layer results in a hump effect and significant negative shifts in the threshold voltage ( V th ) and turn‐on voltage ( V on ), which should be ascribed to the large total carrier number in the channel. The optimal TFT exhibits a high saturated field‐effect mobility of 28.9 cm 2 V −1 s −1 , a near‐zero V th of −0.17 V, a V on of −0.49 V, a low subthreshold swing of 0.12 V dec −1 , a high on‐to‐off current ratio of 3.5 × 10 9 , and a low contact resistance between the source/drain (S/D) electrodes and channel. The TFT also exhibits high stability under bias thermal stress.