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Dual barrier InAlN/AlGaN/GaN‐on‐silicon high‐electron‐mobility transistors with Pt‐ and Ni‐based gate stacks
Author(s) -
Floros Konstantinos,
Li Xu,
Guiney Ivor,
Cho SungJin,
Hemakumara Dilini,
Wallis David J.,
Wasige Edward,
Moran David A. J.,
Humphreys Colin J.,
Thayne Iain G.
Publication year - 2017
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201600835
Subject(s) - transconductance , materials science , optoelectronics , transistor , leakage (economics) , barrier layer , high electron mobility transistor , silicon , layer (electronics) , electrical engineering , nanotechnology , voltage , economics , macroeconomics , engineering
In this work, we report the performance of 3 µm gate length “dual barrier” InAlN/AlGaN/GaN HEMTs on Si substrates with gate–drain contact separations in the range 4–26 µm. Devices with Pt‐ and Ni‐based gates were studied and their leakage characteristics are compared. Maximum drain current I DS of ∼1 A mm −1 , maximum extrinsic transconductance g m ∼203 mS mm −1 and on‐resistance R on ∼4.07 Ω mm for gate to drain distance L GD = 4 µm were achieved. Nearly ideal sub‐threshold swing of ∼65.6 mV dec −1 was obtained for L GD = 14 µm. The use of Pt‐based gate metal stacks led to a two to three orders of magnitude gate leakage current decrease compared to Ni‐based gates. The influence of InAlN layer thickness on the transistor transfer characteristics is also discussed.