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Techniques to reduce thermal resistance in flip‐chip GaN‐based VCSELs
Author(s) -
MishkatUlMasabih Saadat,
Leonard John,
Cohen Daniel,
Nakamura Shuji,
Feezell Daniel
Publication year - 2017
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201600819
Subject(s) - materials science , flip chip , cladding (metalworking) , optoelectronics , thermal resistance , vertical cavity surface emitting laser , chip , thermal , substrate (aquarium) , laser , layer (electronics) , dielectric , optics , composite material , electrical engineering , oceanography , adhesive , physics , geology , meteorology , engineering
The finite element method was used to determine the thermal resistance of a flip‐chip‐bonded GaN‐based vertical‐cavity surface‐emitting laser (VCSEL) with substrate removal and dielectric distributed Bragg reflectors (DBRs). In this work, we investigate the effects of the DBR configuration, mask layer alignment tolerances, aperture diameters, and cladding layer thicknesses on the thermal properties of the flip‐chip design. The current flip‐chip design suffers from high thermal resistance (∼4600 K W −1 ). By reducing the mask layer alignment tolerances and increasing the cladding thickness, the thermal resistance values could be made comparable to devices reported in the literature that achieved CW operation at room temperature (∼3000 K W −1 ). Low thermal resistance designs are critical to achieve CW operation and mitigate the effects of thermal roll‐over in flip‐chip GaN‐based VCSELs.