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Technology development challenges for advanced group IV semiconductor devices
Author(s) -
Claeys Cor,
Arimura Hiro,
Collaert Nadine,
Mitard Jerome,
Rooyackers Rita,
Simoen Eddy,
Vandooren Anne,
Veloso Anabela,
Waldron Niamh,
Witters Liesbeth,
Thean Aaron
Publication year - 2016
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201600494
Subject(s) - power consumption , scalability , computer science , transistor , semiconductor device , key (lock) , scaling , electronic engineering , embedded system , electrical engineering , reliability engineering , power (physics) , engineering , materials science , nanotechnology , voltage , physics , computer security , geometry , mathematics , layer (electronics) , quantum mechanics , database
Advanced devices are not only driven by minimum device geometry, performance enhancement, and cost issues, but also require a low power consumption. Device scaling for higher performance and lower power consumption necessitates the introduction of advanced process modules, new materials new device architectures and, finally, even the use of alternative device operation principles compared to the standard MOS transistor. Several of these advanced devices will be discussed in view of their scalability and their potential for coping with the ITRS roadmap. Key performance parameters will be investigated.