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Performance improvement of charge‐trap memory by using a stacked Zr 0.46 Si 0.54 O 2 /Al 2 O 3 charge‐trapping layer
Author(s) -
Tang Zhenjie,
Li Rong,
Hu Dan,
Zhang Xiwei,
Zhao Yage
Publication year - 2016
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201600143
Subject(s) - trapping , materials science , capacitor , flash memory , annealing (glass) , non volatile memory , optoelectronics , quantum tunnelling , oxide , charge (physics) , trap (plumbing) , analytical chemistry (journal) , voltage , electrical engineering , physics , chemistry , embedded system , computer science , ecology , quantum mechanics , meteorology , metallurgy , composite material , biology , engineering , chromatography
The postdeposition annealing (PDA)‐treated charge‐trap flash memory capacitor with stacked Zr 0.46 Si 0.54 O 2 /Al 2 O 3 charge‐trapping layer flanked by a SiO 2 tunneling oxide and an Al 2 O 3 blocking oxide was fabricated and investigated. It is observed that the memory capacitor exhibits prominent memory characteristics with large memory windows 12.8 V in a ±10 V gate sweeping voltage range, faster program/erase speed, and good data‐retention characteristics even at 125 °C compared to a single charge‐trapping layer (Zr 0.46 Si 0.54 O 2 , Zr 0.79 Si 0.21 O 2 , and Zr 0.46 Al 1.08 O 2.54 ). The quantum wells and introduced interfacial traps of the stacked trapping layer regulate the storage and loss behavior of charges, and jointly contribute to the improved memory characteristics. Hence, the memory capacitor with a stacked trapping layer is a promising candidate in future nonvolatile charge‐trap memory device design and application.