Premium
Bulk transport and contact limitation of MoS 2 multilayer flake transistors untangled via temperature‐dependent transport measurements
Author(s) -
Vladimirov Ilja,
Chow Catherine,
Strudwick AndrewJames,
Kowalsky Wolfgang,
Schwab Matthias Georg,
Kälblein Daniel,
Weitz Ralf Thomas
Publication year - 2015
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201532157
Subject(s) - materials science , semiconductor , molybdenum disulfide , contact resistance , transistor , field effect transistor , optoelectronics , dielectric , nanotechnology , monolayer , conductivity , condensed matter physics , voltage , chemistry , layer (electronics) , composite material , electrical engineering , physics , engineering
Rational use of novel high‐performance semiconductors in field‐effect transistors (FETs) requires exact knowledge of the dominating charge transport mechanisms. In particular, the distinction between contact‐ and semiconductor‐limited transport is important in FETs with small channel lengths. Here, we analyze the relative contributions of contact limitation and intrinsic conductivity of FETs based on mechanically exfoliated multilayers of the high performance n‐type semiconductor molybdenum disulfide (MoS 2 ). Based on a lithography‐free fabrication process, we realize FETs with room temperature mobility ( μ ) of up to 46.8 cm 2 /Vs and I ON / I OFF ratio of up to 10 5 . Using temperature‐ and bias‐dependent charge transport measurements, we are able to show that the intrinsic bulk transport in the flake can be best described by a phonon‐limited band transport model with a conductive bulk at room temperature that freezes out upon cooling of the sample. In addition, we notice an increase of μ by a factor of 2–5 when using a self‐assembled monolayer (SAM)‐modified SiO 2 /MoS 2 interface. More importantly, we show that the choice of drain–source bias ( V DS ) is crucial when interpreting MoS 2 transport measurements, while for large V DS the intrinsic semiconductor transport properties can be observed, a strong contact limitation appears at low V DS . Our combined measurements allow us to distinguish between the effect of bulk and semiconductor/dielectric interface transport and the effect of contact resistance on the electrical transport properties.