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Chemical composition study of high‐ k La‐silicate gate stacks at sub‐nanometer scale
Author(s) -
Liu Fude,
Yang Guandong,
Duscher Gerd
Publication year - 2014
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201431143
Subject(s) - annealing (glass) , high resolution transmission electron microscopy , materials science , gate oxide , gate dielectric , nanometre , transmission electron microscopy , optoelectronics , stack (abstract data type) , analytical chemistry (journal) , oxide , cmos , transistor , metal gate , high κ dielectric , dielectric , electron energy loss spectroscopy , nanotechnology , chemistry , electrical engineering , metallurgy , engineering , chromatography , voltage , computer science , composite material , programming language
La‐based high‐ k oxides as gate dielectrics are promising for the complementary metal–oxide–semiconductor (CMOS) devices. We investigated the chemical compositions across a TaN/LaSiO/Si gate stack at sub‐nanometer scale with electron energy loss spectroscopy (EELS) mapping, Z ‐contrast imaging, high‐resolution transmission electron microscopy (HRTEM) imaging, and other tools. The interfaces in the gate stack were shown to maintain their integrity even after post annealing. The alloying between La 2 O 3 and SiO 2 to form LaSiO depended on the annealing conditions. To the as‐deposited sample, a La–O super atomic layer structure was observed and La was in lower oxidation states as it diffused deeper into SiO 2 . The LaSiO thickness only increased slightly after post annealing and the gate stack showed the required thermal stability. All the results make TaN/LaSiO/Si a promising choice for transistor gate stacks. The combination of EELS mapping and other techniques is very useful in the chemical composition study of gate stacks at ultra‐high spatial resolution.