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Advanced CMOS devices: Challenges and implant solutions
Author(s) -
Colombeau Benjamin,
Guo Baonian,
Gossmann HansJoachim,
Khaja Fareen,
Pradhan Nilay,
Waite Andrew,
Rao K. V.,
Thomidis Christos,
Shim KyuHa,
Henry Todd,
Variam Naushad
Publication year - 2014
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201300169
Subject(s) - scalability , cmos , mosfet , scaling , computer science , electronic engineering , materials science , strain engineering , process (computing) , leakage (economics) , silicon , nanotechnology , electrical engineering , engineering physics , transistor , engineering , optoelectronics , voltage , geometry , mathematics , database , operating system , economics , macroeconomics
In this paper, we first review the trends for advanced CMOS devices in terms of architectures and scalability. The paper highlights the key process challenges for planar MOSFET and FinFET device technologies. We emphasize the need for advanced implant solutions to enable device scaling and performance as well as variability improvement. Especially, we discuss the latest damage engineering solutions as well as materials modification techniques (e.g., contact and strain engineering) to reduce leakage, improve drive current and process margin with reduced variability. Finally, we briefly discuss the implications and new challenges coming from novel channel material devices (e.g., silicon‐germanium, germanium, and III–V).