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Suppression of threshold voltage shifts in organic thin‐film transistors with bilayer gate dielectrics
Author(s) -
Fukuda Kenjiro,
Suzuki Tatsuya,
Kobayashi Takuma,
Kumaki Daisuke,
Tokito Shizuo
Publication year - 2013
Publication title -
physica status solidi (a)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.532
H-Index - 104
eISSN - 1862-6319
pISSN - 1862-6300
DOI - 10.1002/pssa.201228811
Subject(s) - threshold voltage , materials science , gate dielectric , thin film transistor , bilayer , pentacene , optoelectronics , negative bias temperature instability , dielectric , parylene , transistor , gate oxide , overdrive voltage , voltage drop , amorphous solid , voltage , layer (electronics) , electrical engineering , nanotechnology , composite material , chemistry , polymer , membrane , biochemistry , organic chemistry , engineering
Bias‐stress effects in pentacene thin‐film transistors (TFT) with parylene‐C and amorphous fluoropolymers as bilayer gate dielectric layers are systematically investigated. The threshold voltage shift can be controlled systematically by changing the thicknesses of the two dielectric layers. The shift is proportional to a proportion of a potential drop between parylene‐C layer to the total potential drop between gate and source electrodes, and the threshold voltage shift can be fitted to a sum of the exponential functions. Devices with optimized thicknesses of the bilayer gate dielectrics show remarkable stability under continuous gate‐bias voltage stress over long periods, demonstrating shifts in threshold voltage of less than 0.5 V after 48 h.